1. Field of the Invention
The present invention relates to Dynamic Random Accessible Memory (DRAM). Moreover, the present invention relates to DRAM fabricated by slightly modifying a conventional logic process. This invention further relates to the on-chip generation of precision voltages for the operation of DRAM embedded or fabricated using a conventional logic process.
2. Related Art
FIG. 1A is a schematic diagram of a conventional DRAM cell 100 that is fabricated using a conventional logic process. FIG. 1B is a cross sectional view of DRAM cell 100. As used herein, a conventional logic process is defined as a semiconductor fabrication process that uses only one layer of polysilicon and provides for either a single-well or twin-well structure. DRAM cell 100 consists of a p-channel MOS access transistor 1 having a gate terminal 9 connected to word line 3, a drain terminal 17 connected to bit line 5, and a source terminal 18 connected to the gate 11 of a p-channel MOS transistor 2. The connection between source terminal 18 and the gate 11 undesirably increases the layout area of DRAM cell 100. P-channel transistor 2 is configured to operate as a charge storage capacitor. The source and drain 19 of transistor 2 are commonly connected. The source, drain and channel of transistor 2 are connected to receive a fixed plate bias voltage Vpp. The Vpp voltage is a positive boosted voltage that is higher than the positive supply voltage Vdd by more than a transistor threshold voltage Vt.
As used herein, the electrode of the charge storage capacitor is defined as the node coupled to the access transistor, and the counter-electrode of the charge storage capacitor is defined as the node coupled to receive a fixed plate bias voltage. Thus, in DRAM cell 100, the gate 11 of transistor 2 forms the electrode of the charge storage capacitor, and the channel region of transistor 2 forms the counter-electrode of the charge storage capacitor.
To improve soft-error-rate sensitivity of DRAM cell 100, the cell is fabricated in an n-well region 14, which is located in a p-type substrate 8. To minimize the sub-threshold leakage of access transistor 1, n-well 14 is biased at the Vpp voltage (at n-type contact region 21). However, such a well bias increases the junction leakage. As a result, the bias voltage of n-well 14 is selected such that the sub-threshold leakage is reduced without significantly increasing the junction leakage. When storing charge in the storage capacitor, bit line 5 is brought to the appropriate level (i.e., Vdd or Vss) and word line 3 is activated to turn on access transistor 1. As a result, the electrode of the storage capacitor is charged. To maximize the stored charge, word line 3 is required to be driven to a negative boosted voltage Vbb that is lower than the supply voltage Vss minus the absolute value of the threshold voltage (Vtp) of access transistor 1.
In the data retention state, access transistor 1 is turned off by driving word line 3 to the Vdd supply voltage. To maximize the charge storage of the capacitor, the counter electrode is biased at the positive boosted voltage Vpp. The plate voltage Vpp is limited by the oxide breakdown voltage of the transistor 2 forming the charge storage capacitor.
DRAM cell 100 and its variations are documented in U.S. Pat. No. 5,600,598, entitled xe2x80x9cMemory Cell and Wordline Driver For Embedded DRAM in ASIC Process,xe2x80x9d by K. Skjaveland, R. Township, P. Gillingham (hereinafter referred to as xe2x80x9cSkjaveland et al.xe2x80x9d), and xe2x80x9cA 768 k Embedded DRAM for 1.244 Gb.s ATM Switch in a 0.8 um Logic Process,xe2x80x9d P. Gillingham, B. Hold, I. Mes, C. O""Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow, Digest of ISSCC, 1996, pp. 262-263 (hereinafter referred to as xe2x80x9cGillingham et al.). Both Skjaveland et al. and Gillingham et al. describe memory cells that are contained in an n-well formed in a p-type substrate.
FIG. 2 is a schematic diagram of a word line control circuit 200 including a word line driver circuit 201 and a word line boost generator 202 described by Gillingham et al. Word line control circuit 200 includes p-channel transistors 211-217, inverters 221-229, NAND gates 231-232 and NOR gate 241, which are connected as illustrated. Word line driver 201 includes p-channel pull up transistor 211, which enables an associated word line to be pulled up to the Vdd supply voltage. P-channel pull down transistors 212-217 are provided so that the word line can be boosted down to a negative voltage (i.e., xe2x88x921.5V) substantially below the negative supply voltage Vss. However, the p-channel pull down transistors 212-217 have a drive capability much smaller (approximately half) than an NMOS transistor of similar size. As a result, the word line turn on of Gillingham et al. is relatively slow ( greater than 10 ns). Furthermore, in the data retention state, word line driver 201 only drives the word line to the Vdd supply voltage. As a result, the sub-threshold leakage of the access transistor in the memory cells may not be adequately suppressed.
DRAM cells similar to DRAM cell 100 have also been formed using n-channel transistors fabricated in a p-type well region. To maximize stored charge in such n-channel DRAM cells during memory cell access, the associated word line is driven to a voltage higher than the supply voltage Vdd plus the absolute value of the threshold voltage (Vtn) of the access transistor. In the data retention state, the n-channel access transistor is turned off by driving the word line to Vss supply voltage (0 Volts). To maximize the charge storage of the capacitor in an n-channel DRAM cell, the counter electrode is biased at a plate voltage Vbb that is lower than the Vss supply voltage.
A prior art scheme using n-channel DRAM cells includes the one described by Hashimoto et al. in xe2x80x9cAn Embedded DRAM Module using a Dual Sense Amplifier Architecture in a Logic Processxe2x80x9d, 1997 IEEE International Solid-State Circuits Conference, pp. 64-65 and 431. A p-type substrate is used, such that the memory cells are directly in contact with the substrate and are not isolated by any well structure. In the described design, substrate bias is not permitted. Moreover, application of a negative voltage to the word line is not applicable to ASICs that restrict substrate biasing to be zero. Consequently, the architecture achieves a negative gate-to-source voltage (Vgs) by limiting bit line swing. The negative Vgs voltage reduces sub-threshold leakage in the memory cells. Hashimoto et al. fails to describe the structure of the word line driver.
It would therefore be desirable to have a word line driver circuit that improves the leakage currents in DRAM cells fabricated using a conventional logic process. Moreover, it would be desirable to have improved methods for biasing DRAM cells fabricated using a conventional logic process.
Accordingly, the present invention provides a memory system that includes a dynamic random access memory (DRAM) cell, a word line, and a CMOS word line driver fabricated using a conventional logic process. In a particular variation of this embodiment, the DRAM cell includes an access transistor having a thin gate oxide and a capacitor structure having a thick gate oxide of the type typcially used in high voltage I/O devices.
In other embodiments of the present invention, a DRAM cell is fabricated by slightly modifying a conventional logic process. In one such embodiment, the DRAM cell is fabricated by fabricating a crown electrode and a plate electrode of the DRAM cell substantially in a recessed area below the surface of a silicon wafer. The crown and plate electrodes are fabricated prior to the formation of the gate electrode of the access transistor. The recessed area can be formed by etching into a buried field oxide layer. The recessed area in the field oxide is located adjacent to an exposed portion of the silicon wafer. The crown electrode is formed over the recessed area of the field oxide and the exposed portion of the silicon wafer. Out-diffusion from the crown electrode causes a doped contact region to be formed in the previously exposed portion of the silicon wafer. The crown electrode includes a base region located at the bottom of the recessed area, and sidewalls that extend up walls of the recessed area. A dielectric layer is located over the crown electrode. The plate electrode is located over the dielectric layer, thereby completing the capacitor of the DRAM cell. The plate electrode extends over the base region and the sidewalls of the crown electrode.
After the capacitor has been formed, a gate dielectric layer for the access transistor is thermally grown. The access transistor is then formed over the gate dielectric using conventional logic process steps. The access transistor is positioned such that the source of the access transistor is continuous with the doped contact region, thereby coupling the access transistor to the capacitor. The configuration of the storage electrode and the plate electrode advantageously results in a DRAM cell having a high capacitance, a small layout area and a reduced surface topography. This configuration further requires only minimal modifications to a conventional logic process. More specifically, two additional masking steps and two additional polysilicon layers are used to form the capacitor. The temperature cycles associated with the capacitor formation do not subsequently affect the formation of N+ and P+ shallow junctions or the formation of salicide during fabrication of the access transistor. In addition, the internal node of the capacitor is substantially free of salicide for reduced leakage current.
In a variation of this embodiment, the crown electrode and the gate electrode are both formed from the same polysilicon layer.
In yet another embodiment of the present invention, the DRAM cell includes a capacitor structure that extends into a cavity formed in a field dielectric layer, thereby giving the capacitor structure a relatively large surface area and a relatively small layout area. In one embodiment, adding only one masking step to a conventional logic process, the capacitor structure is fabricated as follows. A field dielectric layer (e.g., field oxide) is formed in a semiconductor substrate having a first conductivity type. The field dielectric layer extends below an upper surface of the semiconductor substrate. A cavity is formed in the field dielectric layer by etching the field dielectric layer through an opening in a mask. The cavity extends below the upper surface of the substrate. A threshold adjustment implant can then be optionally performed through the opening of the same mask, thereby forming a threshold adjustment region in the substrate. The threshold adjustment region extends along the upper surface of the substrate, and along the exposed surface of the cavity.
The mask is removed and a gate dielectric layer is formed over the resulting structure. The standard polysilicon gate layer is then formed over the gate dielectric layer, wherein a portion of the polysilicon layer fills the inside of the cavity. The polysilicon layer is then patterned to form a capacitor electrode of the capacitor structure, and a gate electrode of the access transistor. The capacitor electrode has a section that extends over the upper surface of the substrate, and a section that extends into the cavity. In one embodiment, the gate dielectric layer can have different compositions under the gate electrode and under the capacitor electrode.
The word line driver is controlled to selectively provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell.
A positive boosted voltage generator is provided to generate the positive boosted voltage, such that the positive boosted voltage is greater than the Vdd supply voltage but less than the Vdd supply voltage plus one diode voltage drop (Vj) of about 0.6 Volts.
Similarly, a negative boosted voltage generator is provided to generate the negative boosted voltage, such that the negative boosted voltage is less than the Vss supply voltage, but greater than the VSS supply voltage minus one diode voltage drop (Vj) of about 0.6 Volts.
A coupling circuit is provided between the word line driver and one of the positive or negative boosted voltage generators. For example, if the DRAM cell is constructed from PMOS transistors, then the coupling circuit couples the word line driver to the negative boosted word line generator. When the DRAM cell is being accessed, the coupling circuit couples the word line driver to the negative boosted voltage, thereby turning on the p-channel access transistor of the DRAM cell.
Conversely, if the DRAM cell is constructed from NMOS transistors, then the coupling circuit couples the word line driver to the positive boosted word line generator. When the DRAM cell is being accessed, the coupling circuit couples the word line driver to the positive boosted voltage, thereby turning on the n-channel access transistor of the DRAM cell.
The positive boosted voltage generator includes a charge pump control circuit that limits the positive boosted voltage to a voltage less than Vdd plus one diode voltage drop, Vj. Similarly, the negative boosted voltage generator includes a charge pump control circuit that limits the negative boosted voltage to a voltage greater than Vss minus one diode voltage drop, Vj. In a particular embodiment, the positive boosted voltage and the negative boosted voltage are referenced to transistor threshold voltages.
In deep sub-micron logic processes having transistors with gate lengths equal to or less than 0.15 microns, the threshold voltage of the thin oxide transistors is less than 0.5 Volts. This threshold voltage is less than the P-N junction voltage of about 0.6 Volts. During a restore or write operation, the negative boosted voltage is applied to the gate of the access transistor (i.e., the cell word line) through an n-channel driver transistor, which is formed in a p-type substrate. The negative boosted voltage helps to charge the storage capacitor to a voltage substantially close to the Vss supply voltage during the restore or write operation. Theoretically, the negative boosted voltage should be at least one p-channel threshold voltage (plus the additional threshold voltage shift due to body effect) below Vss to charge the electrode of the storage capacitor to a voltage equal to Vss. However, in a logic process where the p-substrate is biased at the Vss potential, applying a bias equal to or less than 0.6 V to the source of the n-channel driver transistor will cause the N+ source junction of the n-channel transistor to turn on. As a result, large substrate current will flow from the negative boosted voltage generator to the substrate, thereby wasting power and increasing the possibility of latch-up. It is important to choose the absolute voltage of a negative boosted voltage to be substantially equal to the absolute value of the threshold voltage of a p-channel transistor (Vtp), but smaller than the turn on voltage of a P-N junction. For example, a negative boosted voltage between 0.3 and 0.4 Volts may be used in processes having a Vtp of 0.5 Volts or less.
The present invention will be more fully understood in view of the following description and drawings.